a) Field of the Invention
The present invention relates to a liquid crystal display (LCD), a testing method thereof and a manufacturing method thereof.
b) Description of Related Art
Liquid crystal displays (LCDs) are the most commonly used flat panel displays (FPDs) handy to carry.
A typical liquid crystal display (LCD) includes a pair of panels having field-generating electrodes and polarizers, and a liquid crystal layer having dielectric anisotropy, which is interposed between the two panels and subject to electric field generated by the electrodes. The variation of the field strength changes molecular orientations of the liquid crystal layer, which tend to align parallel or perpendicular to the field direction. The LCD passes light through the liquid crystal layer via the polarizers and re-orients the liquid crystal molecules to change the polarization of the light. The polarizers convert the change of the polarization into the change of the light transmittance and enable to obtain desired images.
Pluralities of gate lines and data lines are respectively arranged in row and column directions on a panel that has TFTs formed thereon. Pixel electrodes are connected to the gate lines and data lines through the TFTs. The TFT controls transmission of data signal to the pixel electrode under the control of a gate signal received through the gate line. The gate signal is produced at a plurality of gate driving ICs (integrated circuits). The gate driving IC receives a gate-on voltage and a gate-off voltage from a driving voltage generator having one or more DC/DC converters, and combines them to produce the gate signal under the control of a signal controller. The data signal is produced at a plurality of data driving ICs by converting image signal of the signal controller to analogue voltage.
The signal controller, the driving voltage generators, etc. are provided on a printed circuit board (PCB) that is usually disposed to the outside of the panel, and the driving ICs are arranged on a flexible printed circuit (FPC) film disposed between the panel and the PCB. An LCD is usually provided with two PCBs, where one is disposed at an upper side of the panel, and the other at a left side thereof. The left one is called as a gate PCB, and the upper one is called a data PCB. The gate driving ICs, being disposed between the gate PCB and the panel, receive signals from the gate PCB, and the data driving ICs, being disposed between the data PCB and the panel, receive signals from the data PCB.
Such a gate PCB may be dismissed such that only the data PCB is adopted. In this case, the positions of the gate side FPC film and the gate driving ICs formed thereon may be remained. In the case that such a gate PCB is dismissed, separate wire should be provided on the data FPC film and the panel as well as on the gate FPC film, in order to enable transmission of signals from the signal controller, driving voltage generator, etc. to every gate driving IC.
Furthermore, the gate driving ICs may be formed directly on a liquid crystal panel assembly (chip on glass—COG-type) such that a gate side FPC film may also be dismissed. In this case, separate wire should be provided on the data FPC film and the panel.
Meanwhile, a visual inspection (VI) test is executed to inspect operation of a manufactured LCD. For a VI test of an LCD having the above-described structure, additional test wire and test pad connected to the gate line should be prepared at the panel. The size of the test pad should be more than a predetermined dimension, e.g., 800 μm×800 μm, to ensure sufficient reliability of the VI test.
However, rooms for the test wire and test pad is becoming insufficient since the size of an LCD is tried to be reduced, and accordingly difficulty in VI test is increasing.
On the other hand, even if there is enough room for the test wire and the test pad, signal wire arrangement should be altered in order to prevent interference therebetween.
The alteration of signal wire for VI test may cause lengthening of lines in signal wire and increasing of wire resistance, and accordingly, may adversely influence normal signal transmission. Time delay that is increased due to distance between the gate line and the test pad may also deteriorate accuracy of the VI test.